FPGA Implementation and Comparative Analysis of 16-bit ALU Architectures Using Ripple Carry, Carry Look-Ahead, and Carry Select Adders

Abstract

The Arithmetic Logic Unit (ALU) is one of the most important units of the digital systems of the modern era, which performs arithmetic and logical operations. The efficiency of an inner adder architecture of an ALU has a significant effect on the performance of the latter. This paper is the design, FPGA implementation and comparative analysis of three Ripple Carry Adder (RCA) based 16-bit ALU architecture, Carry Look-Ahead Adder (CLA) based architecture, and Carry Select Adder (CSLA) architecture.

The suggested designs are programmed in Verilog HDL and synthesized on a Xilinx Kintex-7 FPGA (xc7k70tfbv676-1) with Vivado 2023.1. In addition, a hybrid CLA-CSLA architecture is implemented to improve computational speed, and operand isolation is applied to reduce switching activity and enhance power efficiency.

They have been experimentally demonstrated to be the smallest-area, consuming 73 LUTs, compared to 109 and 111 LUTs used by CSLA and CLA structures respectively. Nonetheless, Although the Simple ALU shows higher timing slack due to FPGA carry-chain optimization, CLA and CSLA architectures provide improved carry computation efficiency and better scalability for high-speed arithmetic operations. Power analysis shows that they all work at below 0.1 W power, with the CLA-based ALU having the lowest power consumption.

The paper discusses various trade-offs between area, speed, and power, and shows that optimized adder architectures can be used to achieve a high improved performance of the ALU in an FPGA-led system.